The present invention relates generally to a semiconductor integrated circuit device including a scan flip-flop and more particularly to a semiconductor integrated circuit device including a scan flip flop to be used in testing the semiconductor integrated circuit device.
It has become difficult to test recent semiconductor integrated circuit devices (hereinafter referred to as xe2x80x9cLSI""sxe2x80x9d) due to such LSI""s having high integration and an increased number of input terminals. A technique for achieving testability of an LSI is by implementing a scan path method. A scan path method includes designing flip-flop circuits (scan flip-flops) that operate as shift registers. In this way, values stored in a scan flip-flop can be arbitrarily controlled and sampled by, for example, a tester at predetermined times by utilizing a shifting function.
To test an LSI by using a scan path method, the LSI is internally provided with a plurality of scan flip-flops. The scan flip-flops act as flip-flops and are used in a normal operation and in a scan test operation of the LSI. The input and output terminals of the scan flip-flops are serially connected (i.e., concatenated) to form a shift register circuit.
Each scan flip-flop is a circuit including a scan test operation function and a normal operation function. In a scan test operation function, the scan flip-flip acts as a flip-flop based on a data input from a scan-in signal SIN providing a test pattern signal to be latched based on a scan clock SC used as a test clock. In a normal operation function, a scan flip-flop acts as a normal flip-flop.
Scan flip-flops can be edge triggered. Scan flip-flops that operate off a rising clock edge are called a xe2x80x9cpositive F/F (flip-flop)xe2x80x9d and scan flip-flops that operate off a falling clock edge are called a xe2x80x9cnegative F/F (flip-flop)xe2x80x9d.
FIG. 4 is a circuit schematic diagram of a conventional scan flip-flop given the general reference character 400. Conventional scan flip-flop 400 is a positive F/F and is hereinafter referred to as a conventional positive scan F/F 400.
Referring now to FIG. 4, conventional positive scan flip-flop 400 includes a first master latching circuit 1, a second master latching circuit 2, a slave latching circuit 3, and a clock circuit 4. First master latching circuit 1 is used in a normal operation. Second master latching circuit 2 is used in a scan test operation. Slave latching circuit 3 is commonly used in the normal operation and the scan test operation. Clock circuit 4 generates signals for controlling the first master latching circuit 1, second master latching circuit 2, and the slave latching circuit 3 in accordance with a normal operation clock CLK, a first scan clock SC1, and a second scan clock SC2.
Clock circuit 4 includes inverters (IV41 to IV46). Inverter INV41 receives normal operation clock CLK as an input and provides an inverted normal operation clock at terminal AB. Inverter INV42 has an input connected to terminal AB and provides a normal operation clock at terminal A. Inverter INV43 receives first scan clock SC1 as an input and provides an inverted first scan clock at terminal S1B. Inverter INV44 has an input connected to terminal S2B and provides a first scan clock at terminal S1. Inverter INV45 receives second scan clock SC2 as an input and provides an inverted second scan clock at terminal S2B. Inverter INV46 has an input connected to terminal S2B and provides a second scan clock at terminal S2.
First master latching circuit 1 includes transfer gates (TG11 to TG13) and inverters (INV11 and INV12). Transfer gate TG11 is connected between an input terminal receiving input data D and an input of inverter INV11. Transfer gate TG11 receives inverted normal operation clock from terminal AB and normal operation clock from terminal A as control signals. Transfer gate TG12 is connected between an output of inverter INV11 and an input of slave latching circuit 3 (at an input of inverter INV31). Transfer gate TG12 receives inverted normal operation clock from terminal AB and normal operation clock from terminal A as control signals. Inverter INV12 has an input connected to receive an output of inverter INV11. Transfer gate TG13 is connected between an output of inverter INV12 and an input of inverter INV11. Transfer gate TG13 receives inverted normal operation clock from terminal AB and normal operation clock from terminal A as control signals. Transfer gate TG11 is turned on when normal operation clock CLK has a low logic level and turned off when normal operation clock CLK has a high logic level. Transfer gates (TG12 and TG13) are turned on when normal operation clock CLK has a high logic level and turned off when normal operation clock CLK has a low logic level.
Second master latching circuit 2 includes transfer gates (TG21 to TG23) and inverters (INV21 and INV22). Transfer gate TG21 is connected between an input terminal receiving a scan-in signal SIN and an input of inverter INV21. Transfer gate TG21 receives inverted first scan clock from terminal S1B and first scan clock from terminal S1 as control signals. Transfer gate TG22 is connected between an input of inverter INV21 and an output terminal providing output signal Q. Transfer gate TG22 receives inverted second scan clock from terminal S2B and second scan clock from terminal S2 as control signals. Inverter INV21 has an output connected to an input of inverter INV22. Transfer gate TG23 is connected between an output of inverter INV22 and an input of inverter INV21. Transfer gate TG22 receives inverted first scan clock from terminal S1B and first scan clock from terminal S1 as control signals. Transfer gate TG21 is turned on when first scan clock SC1 has a high logic level and turned off when first scan clock SC1 has a low logic level. Transfer gate TG22 is turned on when second scan clock SC2 has a high logic level and turned off when second scan clock SC2 has a low logic level. Transfer gate TG23 is turned on when first scan clock SC1 has a low logic level and turned off when first scan clock SC1 has a high logic level.
Slave latching circuit 3 includes transfer gates (TG31 and TG32) and inverters (INV31 and INV32). Inverter INV31 has an input connected to receive an output from first master latching circuit 1. Transfer gate TG31 is connected between an output of inverter INV31 and a terminal providing output signal Q. Inverter INV32 has an input connected to receive output signal Q. Transfer gate TG32 is connected between an output of inverter INV32 and an input of inverter INV31. Transfer gate TG31 is turned on when second scan clock SC2 has a low logic level and turned off when second scan clock SC2 has a high logic level. Transfer gate TG32 is turned on when normal operation clock CLK has a low logic level and turned off when normal operation clock CLK has a high logic level.
Slave latching circuit 3 has an output (i.e., the output of transfer gate TG31) commonly connected with an output (i.e., the output of transfer gate TG22) of second master latching circuit 2. In this way, data Q is provided from transfer gate TG22 in synchronism with a rising edge of second scan clock SC2 when operating in a scan mode of operation.
The operation of conventional positive scan flip-flop 400 will now be explained.
First a normal operation will be explained.
In a normal operation of conventional positive scan flip-flop 400, first scan clock SC1 is at a xe2x80x9c0xe2x80x9d (logic low) and second scan clock SC2 is held at a xe2x80x9c0xe2x80x9d (logic low). Thus, transfer gates (TG21 and TG22) in second master latching circuit 2 are both turned off. Transfer gate TG23 in second master latching circuit 2 is turned on. Transfer gate TG31 in slave latching circuit 3 is turned on.
Then, when normal operation clock CLK falls (becomes logic low), transfer gate TG11 in first master latching circuit 1 turns on and input data D is fetched into first master latching circuit 1.
Inverter INV11 inverts the receive input data D to provide an output to transfer gate TG12. Inverter INV12 receives the output of inverter INV11 and provides an output to transfer gate TG13. However, with normal operation clock CLK low, transfer gates (TG12 and TG13) are turned off. Thus, first master latching circuit 1 does not provide an output to slave latching circuit 3 at this time.
Then, when normal operation clock CLK rises (becomes logic high), transfer gates (TG12 and TG13) are turned on and transfer gate TG11 is turned off. Thus, the output of inverter INV12 is provided to the input of inverter INV11 to form a latch that maintains the logic value of the input data D provided when normal operation clock CLK was previously low. Further, the output of inverter INV11 is provided to slave latching circuit 3.
Slave latching circuit 3 inverts the output signal provided by first master latching circuit 1 with inverter INV31. As previously described, second scan clock SC2 is low and transfer gate TG31 is turned on. Thus, the output of inverter INV31 is provided as output data Q. Also, output data Q is provided as an input to inverter INV32 which provides an output to transfer gate TG32. However, with normal operation clock CLK high, transfer gate TG32 is turned off.
Upon a subsequent falling edge of normal operation clock CLK, transfer gate TG11 is turned on and the next value of input data D is fetched into first master latching circuit 1. At this time, transfer gate TG12 is turned off, so that an output is not provided from first master latching circuit 1 to slave latching circuit 3. Also at this time, transfer gate TG32 is turned on and output data Q is latched with inverters (INV31 and INV32) in slave latching circuit 3. In this way, output data Q is maintained.
A scan test operation of conventional positive scan flip-flop 400 will now be described.
In the scan test operation, clock CLK is held at a logic low. Thus, transfer gate TG11 in first master latching circuit 1 is turned on. Also, transfer gate TG32 in slave latching circuit 3 is turned on. Transfer gates (TG12 and TG13) of first master latching circuit 1 are respectively turned off.
Then, when first scan clock SC1 rises (becomes logic high), transfer gate TG21 in second master latching circuit 2 turns on and scan input data SIN is fetched into second master latching circuit 2.
Transfer gate TG21 provides the scan input data SIN to inputs of inverter INV21 and transfer gate TG22. Inverter INV21 inverts the input received and provides an inverted output to an input of inverter INV22. Inverter INV22 inverts the input received and provides an inverted output to transfer gate TG23. With first scan clock SC1 high, transfer gate TG23 is turned off. Also, with second scan clock SC2 low, transfer gate TG22 is turned off. Thus, second master latching circuit 2 does not provide a data output Q and data provided as scan input data SIN is not latched in second master latching circuit 2.
Then, when first scan clock SC1 falls (becomes logic low), transfer gate TG21 turns off and transfer gate TG23 is turned on. Thus, the output of inverter INV22 is provided to the input of inverter INV21 to form a latch that maintains the logic value of the scan input data SIN provided when first scan clock SC1 was previously high.
When second scan clock SC2 rises (becomes logic high), transfer gate TG22 of second master latching circuit 2 is turned on. In this way, second master latching circuit 2 provides data output Q. Inverter INV32 in slave latch circuit 3 receives data output Q and provides an inverted output to transfer gate TG32. With normal clock signal CLK low, transfer gate TG32 is turned on. Inverter INV31 thus receives the output from inverter INV32 and provides an inverted output to transfer gate TG31. With second scan clock SC2 high, transfer gate TG31 is turned off. Thus, slave latching circuit 3 does not form a latch at this time.
When second scan clock SC2 falls (becomes low), transfer gate TG22 in second master latching circuit 2 is turned off. However, at this time, transfer gate TG31 in slave latching circuit 3 turns on. In this way, slave latching circuit 3 forms a latch (with inverters INV31 and INV32)) to maintain the value of output data Q.
FIG. 5 is a circuit schematic diagram of a conventional scan flip-flop given the general reference character 500. Conventional scan flip-flop 500 is a negative F/F and is hereinafter referred to as a conventional negative scan F/F 500.
Conventional negative scan flip-flop 500 includes similar constituents as conventional positive scan flip-flop 400. Such constituents are referred to by the same general reference characters.
Conventional negative scan flip-flop 500 includes a first master latching circuit 5, a second master latching circuit 6, a slave latching circuit 7, and a clock circuit 8.
Conventional negative scan flip-flop 500 differs from conventional positive scan flip-flop 400 in that connections of control signals (AB and A) transfer gates (TG11 to TG13) of first master latching circuit 5 in conventional negative scan flip-flop 500 are connected oppositely as compared to first master latching circuit 1 in conventional positive scan flip-flop 400. Also, connections of control signals (AB and A) transfer gate TG32 of slave latching circuit 7 in conventional negative scan flip-flop 500 are connected oppositely as compared to slave latching circuit 3 in conventional positive scan flip-flop 400.
Also, the operation of conventional negative scan flip-flop 500 is the same as the operation of conventional positive scan flip-flop 400, except in the normal operation input data D is fetched into first master latching circuit 5 in response to a rising edge of a normal clock signal CLKB and the fetched data is provided as data output Q in response to a falling edge of normal clock signal CLKB. Also, in a scan test operation is executed, normal clock signal CLKB is held at a logic high.
Thus, a detailed description of the operation of conventional negative scan flip-flop 500 is omitted.
In conventional positive scan flip-flop 400 it is necessary to fix normal clock signal CLK at a logic low to operate in a scan test mode. However, in conventional negative scan flip-flop 500 it is necessary to fix normal clock signal CLKB at a logic high to operate in a scan test mode.
Because normal clock signal CLK must be exclusively set at either a logic high or a logic low, it may be impossible to conduct a scan test when scan flip-flops operating as a positive flip-flop are included on the same LS1 as scan flip-flops operating as a negative flip-flop.
Referring now to FIG. 6, a block schematic diagram of a conventional semiconductor device including conventional scan flip-flops is set forth and given the general reference character 600.
Conventional semiconductor device 600 includes scan flip-flops (602 and 604), an OR gate 606, and an AND gate 608. Scan flip-flop 602 operates as a positive flip-flop and scan flip-flop 604 operates as a negative flip-flop.
A clock CLK is supplied to scan flip-flop 602 by OR gate 606. A clock CLKB is supplied to scan flip-flop 604 by AND gate 608. OR gate 606 receives a control signal SCN at one input and a user clock at another input. AND gate 608 receives a control signal SCNB at one input and a user clock at another input.
Control signal SCN is set to logic high (xe2x80x9c1xe2x80x9d) to fix clock CLK to a logic high for scan flip-flop 606 (a positive flip-flop) to operate in the scan test mode. Control signal SCNB is set to a logic low (xe2x80x9c0xe2x80x9d) to fix clock CLKB to a logic low for scan flip-flop 604 (a negative flip-flop) to operate in the scan test mode.
However, inserting OR gate 606 and/or AND gate 608 in a clock line can increase the difficulty to in optimizing (compensating for) clock skews between flip-flops. In this respect, clock lines themselves are typically designed by using a layout technique, such as a CTS (Clock Tree Synthesis) technique, for optimizing clock skews. However, an existence of logic gates in clock lines makes it difficult to adjust clock skews even when using the CTS technique.
The present embodiments have been set forth to reduce such problems encountered when using the conventional approach.
In view of the above discussion, it would be desirable to provide a scan test flip-flop that may be capable of executing a scan test without obstructing a skew adjustment of clock lines.
According to the present embodiments, a scan flip-flop that may operate as a positive flip-flop or a negative flip-flop in a normal operating mode is disclosed. A scan flip-flop may include a master latching circuit, a slave latching circuit, and a clock circuit. A clock circuit may receive a first signal, a control signal, and a mode signal. A first signal may select between a positive flip-flop operation and a negative flip-flop operation when in a normal operation mode. A mode signal may select between a normal operation mode and a scan test mode. A control signal may disable a first signal so that the scan flip-flop may operate in a known mode, such as a positive flip-flop, regardless as to the value of the first signal. In this way, a scan flip-flop may have reduced logic gates in clock lines as compared to a conventional approach.
According to one aspect of the embodiments, a scan flip-flop may have a normal operation and a scan test operation. The scan flip-flop may include a master latching circuit, a slave latching circuit, and a clock circuit. The master latching circuit may latch a data input in response to a normal clock in the normal operation and may latch a scan-in signal in response to a first scan clock in the scan test operation. The slave latching circuit may provide the latched data input from the master latching circuit in synchronism with the normal clock in the normal operation and may provide the latched scan-in signal from the master latching circuit in synchronism with the second scan clock in the scan test operation. The clock circuit may receive a first switching signal. The first switching signal may set whether the master latching circuit and slave latching circuit operates as a positive flip-flop or a negative flip-flop in the normal operation.
According to another aspect of the embodiments, the clock circuit may receive a control signal that may enable the setting between the positive flip-flop and negative flip-flop operations in accordance with the first switching signal.
According to another aspect of the embodiments, the clock circuit may receive an operation selection signal that selects between the normal operation and the scan test operation.
According to another aspect of the embodiments, the master latching circuit may include a first latch. The first latch may latch the data input in response to the data input in response to the normal clock in the normal operation and may latch the scan-in signal in response to the firs scan clock in the scan test operation.
According to another aspect of the embodiments, the slave latching circuit may provide the latched data input from the master latching circuit at a data output terminal and may provide the latched scan-in signal from the master latching circuit at a scan output terminal.
According to another aspect of the embodiments, when the master latching circuit and slave latching circuit operates as a positive flip-flop, the data input may be latched in the master latching circuit in response to a rising edge of the normal clock. When the master latching circuit and slave latching circuit operates as a negative flip-flop, the data input may be latched in the slave latching circuit in response to a negative edge of the normal clock.
According to another aspect of the embodiments, the slave latching circuit may latch the provided data input in response to the normal clock when a subsequent dta input is being loaded in the master latching circuit.
According to another aspect of the embodiments, a scan flip-flop may have a normal operation for operating as a normal flip-flop receiving data input and a scan test operation for operating as a flip-flop receiving a scan-in signal as a test pattern signal and a first and second scan clock as test clocks. The scan flip-flop may include a master latching circuit, a slave latching circuit, and a clock circuit. The master latching circuit may temporarily hold the data input in response to a normal clock in the normal operation and may temporarily hold the scan-in signal in response to the first scan clock in the scan test operation. The slave latching circuit may output the temporarily held data input in the master latching circuit in response to the normal clock in the normal operation and may output the temporarily held scan-in signal in the master latching circuit in response to the second scan clock in the scan test operation. The clock circuit may receive an externally applied first switching signal and an externally applied second switching signal. The first switching signal may set the master latching circuit and slave latching circuit as one of a positive flip-flop that outputs the temporarily held data input in response to a rising edge of the normal clock or a negative flip-flop that outputs the temporarily held data input in response to a falling edge of the normal clock. The second switching signal may switch the master latching circuit and the slave latching circuit into the normal operation or the scan test operation.
According to another aspect of the embodiments, the clock circuit may receive an externally applied third switching signal that sets the master latching circuit and slave latching circuit as a positive flip-flop irrespectively of a value of the first switching signal.
According to another aspect of the embodiments, the master latching circuit may include a first transfer gate, a second transfer gate, a first gate circuit, a second gate circuit, and a third transfer gate. The first transfer gate may be connected between the input data and a first gate input and may inhibit or allow loading of the input data into the master latching circuit in response to the normal clock. The second transfer gate may be connected between the scan-in signal and the first gate input and may inhibit or allow loading of the scan-in signal into the master latching circuit in response to the first scan clock. The first gate circuit may provide a first gate output. The second gate circuit may receive the first gate output at a second gate input and may provide a second gate output. The third transfer gate may be connected between the second gate output and the first gate input to form a first latch. The first latch may include the first and second gate circuits and the third transfer gate. The second latching circuit may include a fourth transfer gate, a third gate circuit, a fourth gate circuit, and a fifth transfer gate. The fourth transfer gate may be connected between an output of the master latching circuit and a third gate input and may inhibit or allow loading of the output of the master latch into the slave latching circuit in response to the normal clock. The third gate circuit may provide a third gate output. The fourth gate circuit may receive the third gate output at a fourth gate input and may provide a fourth gate output. The fifth transfer gate may be connected between the fourth gate output and the third gate input to form a second latch. The second latch may include the third gate circuit, the fourth gate circuit and the fifth transfer gate.
According to another aspect of the embodiments, the clock circuit may set the master latching circuit and the slave latching circuit as the positive flip-flop or the negative flip-flop by controlling the first transfer gate, second transfer gate, third transfer gate, and fourth transfer gate.
According to another aspect of the embodiments, the clock circuit may include a first logic gate and a second logic gate. The first logic gate may receive the second switching signal, the normal clock, and the first switching signal and may generate a first control signal that sets the master latching circuit and the slave latching circuit as the positive flip-flop in the normal operation. The second logic gate may receive the second switching signal, the normal clock, and the first switching signal and may generate the first control signal that sets the master latching circuit and slave latching circuit as the negative flip-flop in the normal operation. An output of the first logic gate may be fixed by the first switching signal when the master latching circuit and slave latching circuit are collectively set as the negative flip-flop. An output of the second logic gate may be fixed by the first switching signal when the master latching circuit and slave latching circuit are collectively set as the positive flip-flop.
According to another aspect of the embodiments, the clock circuit may receive an externally applied third switching signal that sets the master latching circuit and slave latching circuit as the positive flip-flop irrespectively of the value of the first switching signal.
According to another aspect of the embodiments, when the master latching circuit and slave latching circuit operate as a positive flip-flop, the slave latching circuit may output the temporarily held data input in the master latching circuit in response to a rising edge of the normal clock. When the master latching circuit and slave latching circuit operate as a negative flip-flop, the slave latching circuit may output the temporarily held data input in the master latching circuit in response to a falling edge of the normal clock.
According to another aspect of the embodiments, a semiconductor integrated circuit may include a scan flip-flop and a clock circuit. The scan flip-flop may have a normal mode and a scan test mode. The scan flip-flop may receive a normal data input, a scan data input, and a first clock signal and may provide a normal data output and a scan data output. The clock circuit may receive a normal clock signal, a first control signal, and a scan test signal and may provide the first clock signal. The first control signal may have a positive flip-flop logic level and a negative flip-flop logic level. The scan test signal may have a scan test mode logic level and a normal mode logic level. The scan flip-flop may operate as a positive flip-flop when the first control signal has the positive flip-flop logic level and the scan test signal has the normal mode logic level. The scan flip-flop may operate as a negative flip-flop when the first control signal has the negative flip-flop logic level and the scan test signal has the normal mode logic level.
According to another aspect of the embodiments, the scan flip-flop may include a master latch and a slave latch. The master latch may receive the normal data input and the scan data input and provide a master latch output. The slave latch may receive the master latch output and provide the normal data output and the scan data output.
According to another aspect of the embodiments, the first clock signal may have an inverse logic relationship with respect to the normal clock signal when the scan flip-flop operates as a negative flip-flop and a non-inverse logic relationship with respect to the normal clock signal when the scan flip-flop operates as a positive flip-flop.
According to another aspect of the embodiments, the clock circuit may provide a second clock signal to the scan flip-flop. The first and second clock signals may be complementary.
According to another aspect of the embodiments, the clock circuit may receive a second control signal. The second control signal may have a first logic level and a second logic level. The scan flip-flop may be set as a positive flip-flop irrespective of the first control signal when the second controls signal has the first logic level.
According to another aspect of the embodiments, the scan flip-flop may receive a first scan clock and a normal scan clock. When in the test mode, scan data input may be loaded into the scan flip-flop in response to the first scan clock and scan data output may be provided in response to the second scan clock.